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| ICX205AL Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras Description The ICX205AL is a diagonal 8mm (Type 1/2) interline CCD solid-state image sensor with a square pixel array and 1.45M effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/7.5 second. Also, the adoption of high frame rate readout mode supports 30 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without a mechanical shutter. High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as electronic still cameras, PC input cameras, etc. Features * Progressive scan allows individual readout of the image signals from all pixels. * High horizontal and vertical resolution (both approx. 1024TV-lines) still image without a mechanical shutter. * Supports high frame rate readout mode (effective 256 lines output, 30 frame/s) * Square pixel * Horizontal drive frequency: 14.318MHz * No voltage adjustments (reset gate and substrate bias are not adjusted.) * High resolution, high sensitivity, low dark current * Low smear, excellent antiblooming characteristics * Continuous variable-speed shutter Device Structure * Interline CCD image sensor * Image size: * Total number of pixels: * Number of effective pixels: * Number of active pixels: * Chip size: * Unit cell size: * Optical black: * Number of dummy bits: * Substrate material: 20 pin DIP (Cer-DIP) Pin 1 2 V 8 2 Pin 11 H 40 Optical black position (Top View) Diagonal 8mm (Type 1/2) 1434 (H) x 1050 (V) approx. 1.50M pixels 1392 (H) x 1040 (V) approx. 1.45M pixels 1360 (H) x 1024 (V) approx. 1.40M pixels (7.959mm diagonal) 7.60mm (H) x 6.20mm (V) 4.65m (H) x 4.65m (V) Horizontal (H) direction: Front 2 pixels, rear 40 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels Horizontal 20 Vertical 3 Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98619A99 ICX205AL VOUT GND GND V2B V3 V2A 2 Block Diagram and Pin Configuration (Top View) NC 10 9 8 7 6 5 4 3 Vertical register V1 1 Note) NC NC Horizontal register Note) : Photo sensor 11 12 13 14 15 16 17 18 19 20 CSUB NC SUB VDD Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol V1 V2A V2B V3 NC NC GND NC GND VOUT GND Signal output GND Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Pin No. 11 12 13 14 15 16 17 18 19 20 Symbol VDD GND SUB NC CSUB NC VL RG H1 H2 Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Substrate bias1 Description Supply voltage GND Substrate clock 1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1F. GND -2- RG H1 H2 NC VL ICX205AL Absolute Maximum Ratings Item VDD, VOUT, RG - SUB V2A, V2B - SUB Against SUB V1, V3, VL - SUB H1, H2, GND - SUB CSUB - SUB VDD, VOUT, RG, CSUB - GND Against GND V1, V2A, V2B, V3 - GND H1, H2 - GND Against VL V2A, V2B - VL V1, V3, H1, H2, GND - VL Voltage difference between vertical clock input pins Between input clock pins H1 - H2 H1, H2 - V3 Storage temperature Operating temperature 1 +24V (Max.) when clock width < 10s, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. Ratings -40 to +10 -50 to +15 -50 to +0.3 -40 to +0.3 -25 to -0.3 to +18 -10 to +18 -10 to +15 -0.3 to +28 -0.3 to +15 to +15 -16 to +16 -16 to +16 -30 to +80 -10 to +60 Unit Remarks V V V V V V V V V V V V V C C 1 -3- ICX205AL Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL SUB RG Min. 14.55 Typ. 15.0 1 2 2 Max. 15.45 Unit V Remarks 1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. Typ. 5.5 Max. Unit mA Remarks Clock Voltage Conditions Item Readout clock voltage VVT VVH02A VVH1, VVH2A, VVH2B, VVH3 VVL1, VVL2A, VVL2B, VVL3 Vertical transfer clock voltage V1, V2A, V2B, V3 | VVL1 - VVL3 | VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage VH VHL VRG VRGLH - VRGLL VRGL - VRGLm Substrate clock voltage VSUB 22.15 23.0 4.75 -0.05 3.0 5.0 0 3.3 Symbol Min. 14.55 -0.05 -0.2 -8.4 7.6 Typ. 15.0 0 0 -8.0 8.0 Max. 15.45 0.05 0.05 -7.6 8.4 0.1 0.9 1.3 1.0 0.9 5.25 0.05 5.5 0.4 0.5 23.85 Unit V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Low-level coupling Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL1 + VVL3)/2 VVH = VVH02A Remarks -4- ICX205AL Clock Equivalent Circuit Constant Item Symbol CV1 Capacitance between vertical transfer clock and GND CV2A CV2B CV3 CV12A, CV2B1 Capacitance between vertical transfer clocks CV2A3, CV32B CV13 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND CH1, CH2 CHH CRG CSUB R1 Vertical transfer clock series resistor R2A, R3 R2B Vertical transfer clock ground resistor Horizontal transfer clock series resistor Reset gate clock series resistor V1 CV12A V2A Min. Typ. 2200 1800 6800 3300 1200 1200 2200 47 100 8 680 36 56 43 30 15 20 Max. Unit pF pF pF pF pF pF pF pF pF pF pF Remarks RGND RH RRG R1 R2A RH H1 RH H2 CHH CV2A3 CV13 CH1 CH2 CV1 CV2B1 CV2A CV2B R2B RGND CV3 R3 CV32B V2B V3 Vertical transfer clock equivalent circuit RRG RG Horizontal transfer clock equivalent circuit CRG Reset gate clock equivalent circuit -5- ICX205AL Drive Clock Waveform Conditions (1) Readout clock waveform VT 100% 90% II II M VVT 10% 0% tr twh tf 0V M 2 Note) Readout clock is used by composing vertical transfer clocks V2A and V2B. (2) Vertical transfer clock waveform V1 VVHL VVH1 VVHH VVH VVLH VVL01 VVL1 VVLL V2A, V2B VVH02A, VVH02B VVHH VVHL VVH2A, VVH2B VVH VVL VVLH VVL2A, VVL2B VVLL V3 VVHL VVH3 VVHH VVH VVL VVL03 VVLL VVLH VVL VVH = VVH02A VVL = (VVL01 + VVL03)/2 VVL3 = VVL03 VV1 = VVH1 - VVL01 VV2A = VVH02A - VVL2A VV2B = VVH02B - VVL2B VV3 = VVH3 - VVL03 -6- ICX205AL (3) Horizontal transfer clock waveform tr H2 90 % VCR VH 10 % H1 two VH 2 twl twh tf VHL Cross-point voltage for the H1 rising side of the horizontal transfer clocks H1 and H2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. (4) Reset gate clock waveform tr twh tf RG waveform VRGH twl VRG Point A VRGLH VRGLL VRGLm VRGL VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL. Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% M VSUB 10% 0% M 2 tf VSUB tr twh (A bias generated within the CCD) -7- ICX205AL Clock Switching Characteristics Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V2A, V2B, V3 H1 H2 20 20 twh twl tr tf Unit Remarks Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.5 15 25 25 20 20 25 25 10 10 0.01 0.01 11 13 2.2 51 3 0.5 15 15 10 10 0.01 0.01 3 0.5 s During readout 450 ns 15 15 ns 1 2 During imaging During H1 parallel-serial H2 conversion RG SUB s ns 0.5 s During drain charge Reset gate clock Substrate clock 1 When vertical transfer clock driver CXD1267AN x 2 is used. 2 tf tr - 2ns, and the cross-point voltage (VCR) for the H1 rising side of the H1 and H2 waveforms must be at least VH/2 [V]. Item Horizontal transfer clock Symbol H1, H2 16 two Min. Typ. Max. 20 Unit ns Remarks Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1 0.8 Relative Response 0.6 0.4 0.2 0 400 500 600 700 Wave Length [nm] 800 900 1000 -8- ICX205AL Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Dark signal Dark signal shading Lag Symbol S Vsat Sm SH Vdt Vdt Lag Min. 360 450 0.001 0.0025 20 25 16 4 0.5 Typ. 450 Max. Unit mV mV % % % mV mV % Measurement method 1 2 3 4 4 5 6 7 (Ta = 25C) Remarks 1/30s accumulation Ta = 60C No electronic shutter Zone 0 and I Zone 0 to II' Ta = 60C Ta = 60C Zone Definition of Video Signal Shading 1392 (H) 16 16 8 H 8 V 10 H 8 1040 (V) Zone 0, I Zone II, II' V 10 8 Ignored region Effective pixel region Measurement System CCD signal output [A] CCD C.D.S AMP S/H Signal output [B] Note) Adjust the amplifier gain so that the gain between [A] and [B] equals 1. -9- ICX205AL Image Sensor Characteristics Measurement Method Readout modes The diagram below shows the output methods for the following two readout modes. Progressive scan mode High frame rate readout mode 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT VOUT 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note) Blacked out portions in the diagram indicate pixels which are not read out. Output starts from the line 1 in high frame rate readout mode. 1. Progressive scan mode In this mode, all pixel signals are output in non-interlace format in 1/7.5s. The vertical resolution is approximately 1024TV-lines and all pixel signals within the same exposure period are read out simultaneously, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode All effective areas are scanned in approximately 1/30s by reading out two out of eight lines (1st and 4th lines, 9th and 12th lines). The vertical resolution is approximately 256TV-lines. This readout mode emphasizes processing speed over vertical resolution. - 10 - ICX205AL Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the progressive scan mode, bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value measured at point [B] of the measurement system. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance : 706cd/m2, color temperature of 3200K halogen source) as a subject. (pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (VS) at the center of the screen, and substitute the value into the following formula. S = VS x 250 [mV] 30 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 150mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 150mV. Then after the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) of the signal output and substitute the value into the following formula. Sm = Vsm 1 1 x x 150 500 10 x 100 [%] (1/10V method conversion value) 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 150mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/150 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. - 11 - ICX205AL 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Lag Adjust the signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) x 100 [%] VD V2A Light Strobe light timing Signal output 150mV Output Vlag (Lag) - 12 - Drive Circuit 15V -8.0V 100 XV1 XV2A XSG1 CXD1267AN 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 2SK523 CCD OUT V1 V2A V2B V3 NC NC GND NC GND VOUT 100k 1/35V 20 19 18 17 16 15 14 13 12 11 H2 H1 RG VL NC CSUB NC SUB GND VDD - 13 - 20 19 18 17 16 15 14 13 12 11 22/16V 0.1 0.1 3.9k ICX205 (Bottom View) 0.1 22/20V 0.01 XSUB XV3 XV2B XSG2 1 2 3 4 5 6 7 8 9 10 CXD1267AN 2200P 1M 22/20V H2 H1 RG ICX205AL Sensor Readout Clock Timing Chart Progressive Scan Mode XV1 XV2A/XV2B XV3 XSG1/XSG2 Sensor readout clocks XSG1 and XSG2 are used by composing XV2A and XV2B. - 14 - 139ns (2 bits) 3.49s (50 bits) 55.8s (800 bits) HD V1 V2A/V2B V3 ICX205AL Sensor Readout Clock Timing Chart High Frame Rate Readout Mode XV1 XV2A/XV2B XV3 XSG1 XSG2 Sensor readout clock XSG1 is used by composing XV2A. - 15 - 139ns (2 bits) 55.8s (800 bits) 3.49s (50 bits) 5.0s (72 bits) HD 5.87s (84 bits) V1 V2A V2B V3 14 bits ICX205AL 14 bits Drive Timing Chart (Vertical Sync) Progressive Scan Mode VD HD 6 3 4 1068 1 7 8 9 10 13 1044 1063 11 2 5 12 21 1052 1063 V1 V2A V2B V3 CCD OUT 1040 1038 1039 1040 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 1068 1 - 16 - 1234 56 78 1 2345 ICX205AL Drive Timing Chart (Vertical Sync) High Frame Rate Readout Mode 1/30s 1/30s VD V1 V2A V2B V3 266 267 1 2 3 4 5 6 7 8 CCD OUT 1020 1025 1028 1033 1036 1020 1025 1028 1033 1036 1 4 1 4 9 12 17 20 25 1 4 1 4 9 12 17 20 25 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 HD - 17 - 1 4 1 4 9 12 17 20 25 ICX205AL Drive Timing Chart (Horizontal Sync) Progressive Scan Mode HD 96 392 1 2 412 430 16 CLK H1 H2 V1 96 1 32 1 32 1 64 1 96 1 96 1 96 1 1790 1 56 1 240 - 18 - 96 1 64 1 1 V2A 208 1 V2B 208 V3 1 176 SUB 1 176 RG ICX205AL Drive Timing Chart (Horizontal Sync) High Frame Rate Readout Mode HD 392 1 96 2 412 430 1790 1 CLK H1 H2 42 1 1 1 1 42 1 1 42 1 1 42 1 1 168 42 1 42 42 1 42 112 1 56 42 1 1 42 42 1 14 1 1 42 1 1 42 42 42 42 42 1 42 1 28 1 42 1 1 42 1 42 1 42 42 1 42 1 42 42 42 42 1 1 42 28 16 56 1 - 19 - V1 1 14 V2A 1 1 14 V2B 1 V3 1 28 SUB 1 RG ICX205AL ICX205AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Upper ceramic 39N 29N 29N 0.9Nm Lower ceramic Low melting point glass Shearing strength Tensile strength Torsional strength Compressive strength - 20 - ICX205AL b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to perform the following actions as this may cause cracks. * Applying repeated bending stress to the outer leads. * Heating the outer leads for an extended period with a soldering iron. * Rapidly cooling or heating the package. * Applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools. * Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards. e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. - 21 - Package Outline Unit: mm 20pin DIP (600mil) 0 to 9 9.0 11 (R0.7) 1.4 11 20 A (1.0) (1.7) 0.7 20 ~ 3 C 15.24 1.4 11.55 ~ 3 7.55 V H 15.1 0.3 0.55 B' 0.4 0.83 1.27 1.778 4.0 0.3 0.4 0.8 0.3 M PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY ICX205AL PACKAGE WEIGHT 2.6g ~ - 22 - 0.7 0.46 3.4 0.3 14.6 3 1. "A" is the center of the effective image area. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package is the height reference. 4. The center of the effective image area, relative to "B" and "B'" is (H, V) = (9.0, 7.55) 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom "C" to the effective image area is 1.41 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 60m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. The notch and the hole on the bottom must not be used for reference of fixing. 0.25 1 18.0 0.4 17.6 10 10 1 (4.0) B |
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